DF3048BVX25WV Renesas Electronics America, DF3048BVX25WV Datasheet - Page 568
![MCU 3/5V 128K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048BVX25WV
Manufacturer Part Number
DF3048BVX25WV
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25WV
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 Smart Card Interface
Rev. 3.00 Sep 27, 2006 page 540 of 872
REJ09B0325-0300
TEND
ERS
Retransmission when SCI is in Transmit Mode (see figure 14.12)
(6) After transmitting one frame, if the receiving device returns an error signal, the SCI sets the
(7) The TEND bit in SSR is not set for the frame in which the error signal was received,
(8) If no error signal is returned from the receiving device, the ERS flag is not set in SSR.
(9) If no error signal is returned from the receiving device, transmission of the frame, including
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
TDRE
RDRF
PER
Transfer from TDR to TSR
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is
requested. The ERS flag should be cleared to 0 in SSR before the next parity bit sampling
timing.
indicating an error.
retransmission, is assumed to be complete, and the TEND bit is set to 1 in SSR. If the TIE
bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a
DMA transfer activation source, the next data can be written in TDR automatically. When
the DMAC writes data in TDR, it automatically clears the TDRE bit to 0.
Frame n
Figure 14.12 Retransmission in SCI Transmit Mode
Frame n
Figure 14.11 Retransmission in SCI Receive Mode
DE
(6)
DE
(2)
(1)
(7)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransmitted frame
Retransmitted frame
(DE)
(8)
(DE)
(9)
(4)
(3)
Ds
D0 D1 D2 D3 D4
Ds
Transfer from
TDR to TSR
Frame n + 1
D0 D1 D2 D3 D4
Frame n + 1
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