D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 932
D12350F20IV
Manufacturer Part Number
D12350F20IV
Description
IC H8S/2350 MCU 4.5/5.5V 0+K I-T
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12350F20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Appendix B Internal I/O Register
SSR0—Serial Status Register 0
Rev. 3.00 Sep 15, 2006 page 896 of 988
REJ09B0330-0300
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
Transmit Data Register Empty
0
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
:
:
:
R/(W) *
TDRE
7
1
Receive Data Register Full
0
1
R/(W) *
RDRF
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred
from RSR to RDR
6
0
Overrun Error
0
1
R/(W) *
ORER
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while
RDRF = 1
5
0
Framing Error
0
1
R/(W) *
[Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive
data when reception ends, and the stop bit is 0
FER
4
0
Parity Error
0
1
R/(W) *
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
PER
3
0
Transmit End
0
1
TEND
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte
R
2
1
serial transmit character
and write data to TDR
Multiprocessor Bit
0
1
MPB
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
R
1
0
H'FF7C
Multiprocessor Bit Transfer
0
1
MPBT
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
0
SCI0
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