D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 676

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Smart Card Interface
Retransfer operation when SCI is in transmit mode: Figure 14.12 illustrates the retransfer
operation when the SCI is in transmit mode.
[6] If an error signal is sent back from the receiving end after transmission of one frame is
[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
Rev. 3.00 Sep 15, 2006 page 640 of 988
REJ09B0330-0300
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
is received.
a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE
bit in SCR is enabled at this time, a TXI interrupt request is generated.
If data transfer by the DMAC or DTC by means of the TXI source is enabled, the next data can
be written to TDR automatically. When data is written to TDR by the DMAC or DTC, the
TDRE bit is automatically cleared to 0.
Ds
TDRE
TEND
FER/ERS
Transfer to TSR from TDR
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
nth transfer frame
Figure 14.12 Retransfer Operation in SCI Transmit Mode
[6]
[7]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer to TSR from TDR
Retransferred frame
(DE)
[8]
[9]
Ds D0 D1 D2 D3 D4
Transfer to TSR
from TDR
Transfer
frame n+1