D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 25

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.8
6.9
6.10 Bus Release ....................................................................................................................... 188
6.11 Bus Arbitration.................................................................................................................. 191
6.12 Resets and the Bus Controller ........................................................................................... 193
Section 7 DMA Controller (DMAC)
7.1
7.2
7.3
7.4
7.5
Idle Cycle .......................................................................................................................... 181
6.8.1
6.8.2
Write Data Buffer Function............................................................................................... 187
6.10.1 Overview.............................................................................................................. 188
6.10.2 Operation ............................................................................................................. 188
6.10.3 Pin States in External Bus Released State............................................................ 189
6.10.4 Transition Timing ................................................................................................ 190
6.10.5 Usage Note........................................................................................................... 190
6.11.1 Overview.............................................................................................................. 191
6.11.2 Operation ............................................................................................................. 191
6.11.3 Bus Transfer Timing ............................................................................................ 192
6.11.4 External Bus Release Usage Note........................................................................ 193
Overview........................................................................................................................... 195
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 201
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Register Descriptions (2) (Full Address Mode) ................................................................ 215
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Register Descriptions (3)................................................................................................... 228
7.4.1
7.4.2
7.4.3
Operation........................................................................................................................... 233
Operation ............................................................................................................. 181
Pin States in Idle Cycle ........................................................................................ 186
Features................................................................................................................ 195
Block Diagram ..................................................................................................... 196
Overview of Functions ......................................................................................... 197
Pin Configuration................................................................................................. 199
Register Configuration ......................................................................................... 200
Memory Address Registers (MAR)...................................................................... 202
I/O Address Register (IOAR)............................................................................... 203
Execute Transfer Count Register (ETCR)............................................................ 203
DMA Control Register (DMACR)....................................................................... 205
DMA Band Control Register (DMABCR)........................................................... 209
Memory Address Register (MAR) ....................................................................... 215
I/O Address Register (IOAR)............................................................................... 215
Execute Transfer Count Register (ETCR)............................................................ 216
DMA Control Register (DMACR)....................................................................... 218
DMA Band Control Register (DMABCR)........................................................... 222
DMA Write Enable Register (DMAWER) .......................................................... 228
DMA Terminal Control Register (DMATCR)..................................................... 231
Module Stop Control Register (MSTPCR) .......................................................... 232
............................................................................. 195
Rev. 3.00 Sep 15, 2006 page xxiii of xxxiv