D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 24

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.3
6.4
6.5
6.6
6.7
Rev. 3.00 Sep 15, 2006 page xxii of xxxiv
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Overview of Bus Control .................................................................................................. 142
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Basic Bus Interface ........................................................................................................... 148
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
DRAM Interface................................................................................................................ 161
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 169
6.5.11 Refresh Control .................................................................................................... 172
DMAC Single Address Mode and DRAM Interface......................................................... 176
6.6.1
6.6.2
Burst ROM Interface......................................................................................................... 178
6.7.1
6.7.2
6.7.3
Bus Width Control Register (ABWCR)............................................................... 126
Access State Control Register (ASTCR).............................................................. 127
Wait Control Registers H and L (WCRH, WCRL) .............................................. 128
Bus Control Register H (BCRH).......................................................................... 132
Bus Control Register L (BCRL)........................................................................... 134
Memory Control Register (MCR) ........................................................................ 136
DRAM Control Register (DRAMCR).................................................................. 138
Refresh Timer/Counter (RTCNT)........................................................................ 141
Refresh Time Constant Register (RTCOR).......................................................... 141
Area Partitioning .................................................................................................. 142
Bus Specifications................................................................................................ 143
Memory Interfaces ............................................................................................... 144
Advanced Mode ................................................................................................... 145
Areas in Normal Mode......................................................................................... 146
Chip Select Signals .............................................................................................. 147
Overview.............................................................................................................. 148
Data Size and Data Alignment ............................................................................. 148
Valid Strobes....................................................................................................... 150
Basic Timing........................................................................................................ 151
Wait Control ........................................................................................................ 159
Overview.............................................................................................................. 161
Setting DRAM Space........................................................................................... 161
Address Multiplexing........................................................................................... 162
Data Bus............................................................................................................... 162
Pins Used for DRAM Interface............................................................................ 163
Basic Timing........................................................................................................ 164
Precharge State Control ....................................................................................... 165
Wait Control ........................................................................................................ 166
Byte Access Control............................................................................................. 168
When DDS = 1..................................................................................................... 176
When DDS = 0..................................................................................................... 177
Overview.............................................................................................................. 178
Basic Timing........................................................................................................ 178
Wait Control ........................................................................................................ 180