D12350F20IV Renesas Electronics America, D12350F20IV Datasheet
D12350F20IV
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D12350F20IV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2350 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Rev. 3.00 Sep 15, 2006 page iv of xxxiv ...
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The H8S/2350 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with ...
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Rev. 3.00 Sep 15, 2006 page vi of xxxiv ...
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Main Revisions for This Edition Item Page All — 1.2 Block Diagram 6 Figure 1.1 Block Diagram 5.6.2 Block Diagram 118 Figure 5.9 Interrupt Control for DTC and DMAC 6.1.2 Block Diagram 123 Figure 6.1 Block Diagram of Bus Controller ...
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Item Page 6.8.1 Operation 185 Figure 6.35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) 6.10.4 Transition 190 Timing Figure 6.37 Bus- Released State Transition Timing 7.5.11 DMAC Bus 272 Cycles (Single Address Mode) Figure ...
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Item Page 7.7 Usage Notes 285, 286 DMAC Register Access during Operation Figure 7.40 DMAC Register Update Timing Figure 7.41 Contention between DMAC Register Update and CPU Read 9.3.3 Pin Functions 346 Table 9.5 Port 2 Pin Functions 9.11.3 Pin ...
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Item Page 12.3.3 Timing of 542 Setting Overflow Flag (OVF) Figure 12.6 Timing of Setting of OVF 13.2.8 Bit Rate 564 Register (BRR) Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 14.1 Features 611 14.2.2 Serial Status 617 ...
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Item Page 14.2.2 Serial Status 617 Register (SSR) 14.3.2 Pin Connections 621 Figure 14.2 Schematic Diagram of Smart Card Interface Pin Connections 14.3.4 Register 625 Settings 14.3.6 Data Transfer 631 Operations Figure 14.6 TEND Flag Generation Timing in Transmission Operation ...
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Item Page 15.4.3 Input Sampling 655 and A/D Conversion Timing Figure 15.5 A/D Conversion Timing A.4 Number of States 786 Required for Instruction Execution Table A.5 Number of Cycles in Instruction Execution Rev. 3.00 Sep 15, 2006 page xii of ...
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Item Page A.5 Bus States during 795 Instruction Execution Table A.6 Instruction Execution Cycles Revision (See Manual for Details) Table A.6 amended Rev. 3.00 Sep 15, 2006 page xiii of xxxiv ...
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Item Page A.5 Bus States during 799 Instruction Execution Table A.6 Instruction Execution Cycles Rev. 3.00 Sep 15, 2006 page xiv of xxxiv Revision (See Manual for Details) Table A.6 amended ...
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Item Page B.1 Addresses 812 813 B.2 Functions 821 842 Revision (See Manual for Details) Table amended Address Register (low) Name 2 PAPCR * H'FF70 2 PBPCR * H'FF71 2 PCPCR * H'FF72 2 PDPCR * H'FF73 PEPCR * 2 ...
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Item Page B.2 Functions 846 923 924 C.13 Port G Block 975 Diagram Figure C.13 (c-2) H8S/2350 Port G Block Diagram (Pin PG4) D.2 Port States in Each 980 Mode [H8S/2350] Table D.2 I/O Port 981 States in Each 982 ...
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Item Page H. Package 987 Dimensions Figure H.1 TFP-120 Package Dimensions Figure H.2 TFP-128 987 Package Dimensions Revision (See Manual for Details) Figure H.1 replaced Figure H.2 replaced Rev. 3.00 Sep 15, 2006 page xvii of xxxiv ...
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Rev. 3.00 Sep 15, 2006 page xviii of xxxiv ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 14 Section 2 CPU ...................................................................................................................... 21 2.1 Overview........................................................................................................................... 21 2.1.1 Features................................................................................................................ ...
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Power-Down State ............................................................................................... 64 2.9 Basic Timing ..................................................................................................................... 65 2.9.1 Overview.............................................................................................................. 65 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 65 2.9.3 On-Chip Supporting Module Access Timing....................................................... 67 2.9.4 External Address Space Access Timing............................................................... 68 Section 3 MCU Operating Modes 3.1 ...
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Notes on Use of the Stack ................................................................................................. 89 Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 91 5.1.1 Features................................................................................................................ 91 5.1.2 Block Diagram ..................................................................................................... 92 5.1.3 Pin Configuration................................................................................................. 93 5.1.4 Register Configuration ......................................................................................... 93 5.2 Register Descriptions ........................................................................................................ 94 5.2.1 System ...
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Bus Width Control Register (ABWCR)............................................................... 126 6.2.2 Access State Control Register (ASTCR).............................................................. 127 6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 128 6.2.4 Bus Control Register H (BCRH).......................................................................... 132 6.2.5 Bus Control Register L (BCRL)........................................................................... 134 6.2.6 ...
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Idle Cycle .......................................................................................................................... 181 6.8.1 Operation ............................................................................................................. 181 6.8.2 Pin States in Idle Cycle ........................................................................................ 186 6.9 Write Data Buffer Function............................................................................................... 187 6.10 Bus Release ....................................................................................................................... 188 6.10.1 Overview.............................................................................................................. 188 6.10.2 Operation ............................................................................................................. 188 6.10.3 Pin States in External ...
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Transfer Modes .................................................................................................... 233 7.5.2 Sequential Mode .................................................................................................. 236 7.5.3 Idle Mode............................................................................................................. 239 7.5.4 Repeat Mode ........................................................................................................ 242 7.5.5 Single Address Mode ........................................................................................... 246 7.5.6 Normal Mode ....................................................................................................... 249 7.5.7 Block Transfer Mode ........................................................................................... 252 7.5.8 DMAC Activation Sources ...
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Normal Mode ....................................................................................................... 309 8.3.6 Repeat Mode ........................................................................................................ 310 8.3.7 Block Transfer Mode ........................................................................................... 311 8.3.8 Chain Transfer ..................................................................................................... 313 8.3.9 Operation Timing................................................................................................. 314 8.3.10 Number of DTC Execution States........................................................................ 315 8.3.11 Procedures for Using DTC................................................................................... 317 8.3.12 Examples ...
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MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 374 9.9 Port B ................................................................................................................................ 375 9.9.1 Overview.............................................................................................................. 375 9.9.2 Register Configuration [H8S/2351 Only] ............................................................ 376 9.9.3 Pin Functions ....................................................................................................... 378 9.9.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 380 9.10 Port ...
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Timer Status Register (TSR) ................................................................................ 443 10.2.6 Timer Counter (TCNT)........................................................................................ 447 10.2.7 Timer General Register (TGR) ............................................................................ 448 10.2.8 Timer Start Register (TSTR)................................................................................ 449 10.2.9 Timer Synchro Register (TSYR).......................................................................... 450 10.2.10 Module Stop Control Register (MSTPCR) .......................................................... 451 10.3 ...
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Module Stop Control Register (MSTPCR) .......................................................... 519 11.3 Operation........................................................................................................................... 520 11.3.1 Overview.............................................................................................................. 520 11.3.2 Output Timing...................................................................................................... 521 11.3.3 Normal Pulse Output............................................................................................ 522 11.3.4 Non-Overlapping Pulse Output............................................................................ 524 11.3.5 Inverted Pulse Output........................................................................................... 527 11.3.6 Pulse Output Triggered by Input Capture ...
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Receive Shift Register (RSR)............................................................................... 550 13.2.2 Receive Data Register (RDR) .............................................................................. 550 13.2.3 Transmit Shift Register (TSR) ............................................................................. 551 13.2.4 Transmit Data Register (TDR)............................................................................. 551 13.2.5 Serial Mode Register (SMR)................................................................................ 552 13.2.6 Serial Control Register (SCR).............................................................................. 555 13.2.7 Serial ...
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Features................................................................................................................ 641 15.1.2 Block Diagram ..................................................................................................... 642 15.1.3 Pin Configuration................................................................................................. 643 15.1.4 Register Configuration ......................................................................................... 645 15.2 Register Descriptions ........................................................................................................ 645 15.2.1 A/D Data Registers (ADDRA to ADDRD) .............................................. 645 15.2.2 A/D Control/Status Register (ADCSR)................................................................ 646 ...
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Block Diagram ..................................................................................................... 675 18.2 Operation........................................................................................................................... 676 Section 19 Clock Pulse Generator 19.1 Overview........................................................................................................................... 677 19.1.1 Block Diagram ..................................................................................................... 677 19.1.2 Register Configuration ......................................................................................... 678 19.2 Register Descriptions ........................................................................................................ 678 19.2.1 System Clock Control Register (SCKCR)............................................................ 678 19.3 Oscillator........................................................................................................................... ...
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DC Characteristics ............................................................................................................ 702 21.3 AC Characteristics ............................................................................................................ 707 21.3.1 Clock Timing ....................................................................................................... 708 21.3.2 Control Signal Timing.......................................................................................... 710 21.3.3 Bus Timing........................................................................................................... 712 21.3.4 DMAC Timing..................................................................................................... 722 21.3.5 Timing of On-Chip Supporting Modules ............................................................. 726 21.4 A/D Conversion Characteristics ...
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Appendix E Pin States at Power-On E.1 When Pins Settle from an Indeterminate State at Power-On ............................................. 983 E.2 When Pins Settle from the High-Impedance State at Power-On ....................................... 984 Appendix F Timing of Transition to and Recovery from Hardware ...
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Rev. 3.00 Sep 15, 2006 page xxxiv of xxxiv ...
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Overview The H8S/2350 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with ...
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Section 1 Overview Table 1.1 Overview Item Specification CPU General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit ...
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Item Specification DMA controller Choice of short address mode or full address mode (DMAC) 4 channels in short address mode 2 channels in full address mode Transfer possible in repeat mode, block transfer mode, etc. Single address mode transfer possible ...
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Section 1 Overview Item Specification I/O ports 87 I/O pins, 8 input-only pins Memory Mask ROM High-speed static RAM Product Name H8S/2350 H8S/2351 Nine external interrupt pins (NMI, IRQ0 to IRQ7) Interrupt controller 42 internal interrupt sources Eight priority levels ...
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Item Specification Clock pulse Built-in duty correction circuit generator Packages 120-pin plastic TQFP (TFP-120) 128-pin plastic QFP (FP-128) Product lineup ROMless Version — HD6412350 Model Name Mask ROM Version HD6432351 — Rev. 3.00 Sep 15, 2006 page 5 of 988 ...
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Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the H8S/2350 Group EXTAL XTAL STBY RES WDTOVF NMI ...
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Pin Description 1.3.1 Pin Arrangement Figures 1.2 and 1.3 show the pin arrangement of the H8S/2350 Group ADTRG ref AN0 ...
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Section 1 Overview AV 103 CC V 104 ref P4 /AN0 105 0 P4 /AN1 106 1 P4 /AN2 107 2 P4 /AN3 108 3 P4 /AN4 109 4 P4 /AN5 110 5 P4 /AN6/DA0 111 6 P4 /AN7/DA1 112 ...
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Pin Functions in Each Operating Mode Table 1.2 shows the pin functions of the H8S/2350 Group in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin No. TFP-120 FP-128 Mode ...
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Section 1 Overview Pin No. TFP-120 FP-128 Mode /IRQ6 /IRQ7 /IRQ3 /IRQ2 6 — — ...
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Pin No. TFP-120 FP-128 Mode /RxD0 /RxD1 /SCK0 /SCK1 DREQ0 — ...
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Section 1 Overview Pin No. TFP-120 FP-128 Mode 1 STBY XTAL 78 86 EXTAL ...
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Pin No. TFP-120 FP-128 Mode 1 103 113 AV SS 104 114 V SS 105 115 P1 /PO15/ 7 TIOCB2/ TCLKD 106 116 P1 /PO14/ 6 TIOCA2 107 117 P1 /PO13/ 5 TIOCB1/ TCLKC 108 118 P1 /PO12/ 4 TIOCA1 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions of the H8S/2350 Group. Table 1.3 Pin Functions Type Symbol Power supply Clock XTAL EXTAL Rev. 3.00 Sep 15, 2006 page 14 of 988 ...
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Type Symbol Operating mode control MD 0 RES System control STBY BREQ BREQO BACK Pin No. TFP-120 FP-128 I/O 115 to 125 to Input 113 123 73 81 Input 75 83 Input 88 96 Input 86 94 ...
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Section 1 Overview Type Symbol Interrupts NMI IRQ7 to IRQ0 Address bus Data bus CS7 to Bus control CS0 AS RD HWR LWR Rev. 3.00 Sep 15, 2006 page 16 ...
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Type Symbol CAS Bus control LCAS WAIT DREQ1, DMA controller DREQ0 (DMAC) TEND1, TEND0 DACK1, DACK0 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 Pin No. TFP-120 FP-128 I/O 116 126 Output ...
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Section 1 Overview Type Symbol 16-bit timer- TIOCA3, pulse unit TIOCB3, (TPU) TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Programmable PO15 to pulse generator PO0 (PPG) WDTOVF Watchdog timer (WDT) Serial TxD1, communication TxD0 interface (SCI) RxD1, Smart Card RxD0 interface ...
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Type Symbol A/D converter AV CC and D/A converter ref I/O ports ...
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Section 1 Overview Type Symbol I/O ports ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate 8/16/32-bit register-register add/subtract : 8-bit register-register multiply 16 ÷ 8-bit register-register divide 16 16-bit register-register multiply 32 ÷ 16-bit register-register ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control register, have been added. Expanded address space Normal ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area ...
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Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in ...
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Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception ...
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Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. SP (ER7) 2.4.3 Control Registers The ...
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Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ...
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Section 2 CPU The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * 1 , PUSH * ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction Data MOV BWL BWL BWL BWL BWL BWL transfer ...
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Section 2 CPU Function Instruction System TRAPA — control RTE — SLEEP — LDC B STC — ANDC, ORC, B XORC NOP — Block data transfer — Legend: B: Byte W: Word L: Longword Note: * Cannot be used in ...
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Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source General register * ...
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Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep 15, 2006 page ...
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Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Note: * Size refers to the operand size. B: Byte W: Word L: Longword Size * Function B/W/L Rd ± Rs Rd, Rd ...
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Section 2 CPU Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep 15, 2006 page 44 of 988 REJ09B0330-0300 Size * Function ...
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Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Size refers to the operand size. B: Byte W: Word L: Longword Size * Function B/W Rd, Rd ...
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Section 2 CPU Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Note: * Size refers to the operand size. B: Byte Rev. 3.00 Sep 15, 2006 page 46 of 988 REJ09B0330-0300 Size * Function B ...
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Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Note: * Size refers to the operand size. B: Byte Size * Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with a specified bit in a general ...
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Section 2 CPU Type Instruction Branch Bcc instructions JMP BSR JSR RTS Rev. 3.00 Sep 15, 2006 page 48 of 988 REJ09B0330-0300 Size * Function — Branches to a specified address if a specified condition is true. The branching conditions ...
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Type Instruction System TRAPA control RTE instructions SLEEP LDC STC ANDC ORC XORC NOP Note: * Size refers to the operand size. B: Byte W: Word Size * Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. ...
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Section 2 CPU Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Rev. 3.00 Sep 15, 2006 page 50 of 988 REJ09B0330-0300 Size * Function — if R4L 0 then Repeat @ER5+ R4L–1 R4L Until R4L = 0 else next; — ...
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Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 shows ...
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Section 2 CPU (3) Effective Address Extension Eight, 16 bits specifying immediate data, an absolute address displacement. (4) Condition Field Specifies the branching condition of Bcc instructions. 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing ...
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Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the ...
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Section 2 CPU Table 2.5 indicates the accessible absolute address ranges. Table 2.5 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address (6) Immediate—#xx:8, #xx:16, or ...
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Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Specified Branch address by @aa:8 (a) Normal Mode Figure 2.13 Branch Address Specification in Memory Indirect ...
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Section 2 CPU Table 2.6 Effective Address Calculation Rev. 3.00 Sep 15, 2006 page 56 of 988 REJ09B0330-0300 ...
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Section 2 CPU Rev. 3.00 Sep 15, 2006 page 57 of 988 REJ09B0330-0300 ...
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Section 2 CPU Rev. 3.00 Sep 15, 2006 page 58 of 988 REJ09B0330-0300 ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state ...
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Section 2 CPU End of bus request Bus-released state End of exception handling Exception-handling state RES = high Reset state * 1 From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
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Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI ...
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Normal mode SP CCR CCR * PC (16 bits) (a) Interrupt control mode 0 Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Note: * Ignored when returning. Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 ...
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Section 2 CPU 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts. There ...
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Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred “state.” The memory cycle or bus cycle ...
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Section 2 CPU Address bus AS RD HWR, LWR Data bus Figure 2.18 Pin States during On-Chip Memory Access Rev. 3.00 Sep 15, 2006 page 66 of 988 REJ09B0330-0300 Bus cycle T1 Unchanged High High High High-impedance state ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access ...
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Section 2 CPU Address bus AS RD HWR, LWR Data bus Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 H8S/2350 Operating Mode Selection The H8S/2350 has three operating modes (modes 1, 4, and 5). These modes are determined by the mode pin ( settings. The CPU operating mode ...
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Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The H8S/2350 can be used only in modes 1, 4, and 5. This means that the mode pins must be set to select ...
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The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions 3.2.1 Mode Control Register (MDCR) 7 Bit : — Initial value : 1 R/W : — Note: * Determined by pins MD MDCR is an 8-bit read-only register that indicates the current ...
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Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 Bit ...
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B ...
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Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part ...
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Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports vary depending on the operating mode. Table 3.4 shows their functions in each operating mode. Table 3.4 Pin Functions in ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'F400 On-chip RAM * 2 External address H'FC00 space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Notes: 1. Modes 2 and ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFF400 On-chip RAM * 2 External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. ...
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Table 4.2 Exception Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2350 Group enters the reset state. A reset initializes the internal state of the ...
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Reset Sequence The H8S/2350 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2350 Group is reset, hold the RES pin low for at least power-up. To reset the H8S/2350 ...
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Section 4 Exception Handling RES Address bus RD HWR, LWR (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If ...
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Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 42 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
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Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR * PC (16 bits) (a) Interrupt control mode 0 Note: * ...
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Notes on Use of the Stack When accessing word data or longword data, the H8S/2350 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and ...
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Section 4 Exception Handling Rev. 3.00 Sep 15, 2006 page 90 of 988 REJ09B0330-0300 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2350 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Any of two interrupt control modes can be set by ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request WOVI to TEI ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for ...
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Interrupt Priority Registers (IPRA to IPRK) Bit : 7 — IPR6 Initial value : 0 R/W : — R/W The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels for interrupts ...
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Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA Initial value : 0 R/W : R/W R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA Initial value : 0 R/W : R/W R/W ISCR registers ...
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Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : 7 IRQ7F IRQ6F Initial value : 0 R/(W) * R/(W) * R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (42 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be ...
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Section 5 Interrupt Controller IRQnSCA, IRQnSCB Edge/level detection circuit IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. IRQn input pin IRQnF Figure 5.3 Timing ...
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Internal Interrupts There are 42 sources for internal interrupts from on-chip supporting modules. For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If ...
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Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) CMI (compare match) Reserved ADI (A/D conversion end) ...
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Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B ...
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Section 5 Interrupt Controller Interrupt Source TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) Reserved DEND0A (channel 0/ channel 0A transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/ channel 1A ...
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Interrupt Source ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) Reserved Note: * Lower 16 bits of the start address. 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt ...
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Section 5 Interrupt Controller Table 5.5 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 — — 1 Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 ...
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Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) ...
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Section 5 Interrupt Controller (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, ...
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Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, ...
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Section 5 Interrupt Controller IRQ0 Yes Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Rev. 3.00 Sep 15, 2006 page 110 of 988 REJ09B0330-0300 Program execution status Interrupt generated? Yes Yes NMI Yes No ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5.6 shows a ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Rev. 3.00 Sep 15, 2006 page 112 of 988 REJ09B0330-0300 Program execution status No Interrupt generated? ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The H8S/2350 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM * and the stack area in on-chip RAM, enabling high- ...
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Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch S I Branch address read S J Stack manipulation S K Legend: m: Number of wait states in an external device access. 5.5 Usage Notes 5.5.1 ...
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Section 5 Interrupt Controller TIER0 write cycle by CPU Internal address bus Internal write signal TGIEA TGFA TGI0A interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt ...
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Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With ...
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Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC and DMAC interrupt controller. Interrupt request IRQ interrupt Interrupt source On-chip clear signal supporting module Interrupt controller Figure 5.9 Interrupt Control for DTC and ...
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Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected ...
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Section 5 Interrupt Controller Table 5.11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCEA to DTCEF in the DTC and the ...
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Section 6 Bus Controller 6.1 Overview The H8S/2350 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external ...
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Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 External bus control signals BREQ BACK BREQO WAIT External DRAM signals Figure 6.1 Block Diagram of Bus Controller Area decoder ABWCR ASTCR BCRH BCRL ...
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Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Address strobe Read High write/write enable Low write Chip select 0 Chip select 1 Chip select 2/row address ...
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Name Chip select 7 Upper column address strobe CAS Lower column strobe Wait Bus request Bus request acknowledge Bus request output 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Bus ...
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Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 ABW6 Modes Initial value : R/W Mode 4 Initial value : 0 RW ...
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Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR ...
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Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area is 0 ...
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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller (2) WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller 6.2.4 Bus Control Register H (BCRH) Bit : 7 ICIS1 Initial value : 1 R/W : R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface ...
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Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states Bit 3—Burst Cycle Select 0 (BRSTS0): Selects ...
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Section 6 Bus Controller 6.2.5 Bus Control Register L (BCRL) Bit : 7 BRLE BREQOE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the LCAS signal, ...
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Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface. Bit 3 DDS Description 0 When DMAC single address transfer is performed in DRAM space, full access is always executed DACK signal goes ...
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Section 6 Bus Controller 6.2.6 Memory Control Register (MCR) Bit : 7 TPC Initial value : 0 R/W : R/W MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address ...
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Bit 5 RCDM Description 0 DRAM interface: RAS up mode selected 1 DRAM interface: RAS down mode selected Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas are designated as 8-bit DRAM space, and ...
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Section 6 Bus Controller Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all ...
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Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before- RAS refreshing. Bit 6 RCW Description 0 Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in T cycle Rr 1 One wait state inserted in CAS-before-RAS refreshing ...
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Section 6 Bus Controller Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE ...
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Refresh Timer/Counter (RTCNT) Bit : 7 Initial value : 0 R/W : R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare ...
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Section 6 Bus Controller 6.3 Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 2-Mbyte units, and performs bus control for external space ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL ABWCR ASTCR ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The H8S/2350 Group memory ...
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Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on ...
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Section 6 Bus Controller Area 7 Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the ...
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Chip Select Signals The H8S/2350 Group can output chip select signals (CS0 to CS7) to areas the signal being driven low when the corresponding external space area is accessed. In normal mode, only the CS0 signal ...
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Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data ...
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Access Space Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D 15 amount of data that can be accessed at one time is one byte or one ...
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Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data ...
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Basic Timing 8-Bit 2-State Access Space Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half ( The LWR pin is fixed high. Wait ...
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Section 6 Bus Controller 8-Bit 3-State Access Space Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half ( The LWR pin is fixed high. ...
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Access Space Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D 15 half ( for the odd address ...
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Section 6 Bus Controller Address bus CSn Read HWR LWR Write Note Figure 6.9 Bus Timing for ...
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Address bus CSn Read HWR LWR Write Note Figure 6.10 Bus Timing for ...
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Section 6 Bus Controller 16-Bit 3-State Access Space Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D lower half ( for the ...
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Address bus CSn Read HWR LWR Write Note Figure 6.12 Bus Timing for ...
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Section 6 Bus Controller Address bus CSn Read HWR LWR Write Note Figure ...
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Wait Control When accessing external space, the H8S/2350 Group can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin w wait insertion ...
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Section 6 Bus Controller Figure 6.14 shows an example of wait state insertion timing. WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus indicates the timing of WAIT pin sampling. Note: Figure 6.14 Example of Wait ...
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DRAM Interface 6.5.1 Overview When the H8S/2350 Group is in advanced mode, external space areas can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the ...
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Section 6 Bus Controller 6.5.3 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table ...
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Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 DRAM Interface Pins With DRAM Pin Setting Name HWR WE Write enable LCAS LCAS Lower column address strobe CS2 RAS2 ...
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Section 6 Bus Controller 6.5.6 Basic Timing Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling ...