D12350F20IV Renesas Electronics America, D12350F20IV Datasheet - Page 52

• Manufacturer Part Number: D12350F20IV
• Description: IC H8S/2350 MCU 4.5/5.5V 0+K I-T
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12350F20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview
Rev. 3.00 Sep 15, 2006 page 16 of 988
REJ09B0330-0300
Type
Interrupts
Address bus
Data bus
Bus control
Symbol
NMI
IRQ7 to
IRQ0
A
A
D
D
CS7 to
CS0
AS
RD
HWR
LWR
23
0
15
0
to
to
TFP-120
74
28 to 25,
29 to 32
28 to 25,
23 to 16,
14 to 7,
5 to 2
51 to 48,
46 to 39,
37 to 34
29, 30,
61, 60,
117 to 120
82
83
84
85
Pin No.
FP-128
32 to 29,
33, 34,
37, 38
32 to 29,
27 to 20,
18 to 11,
9 to 6
57 to 54,
52 to 45,
43 to 40
33, 34,
69, 66,
127, 128,
1, 2
90
91
92
93
82
I/O
Input
Input
Output Address bus: These pins output an
I/O
Output Chip select: Signals for selecting
Output Address strobe: When this pin is low,
Output Read: When this pin is low, it
Output High write/write enable:
Output Low write:
Name and Function
Nonmaskable interrupt: Requests a
nonmaskable interrupt. When this pin
is not used, it should be fixed high.
Interrupt request 7 to 0: These pins
request a maskable interrupt.
address.
Data bus: These pins constitute a
bidirectional data bus.
areas 7 to 0.
it indicates that address output on
the address bus is enabled.
indicates that the external address
space can be read.
A strobe signal that writes to external
space and indicates that the upper
half (D
enabled.
The 2CAS type DRAM write enable
signal.
A strobe signal that writes to external
space and indicates that the lower
half (D
enabled.
15
7
to D
to D
0
8
) of the data bus is
) of the data bus is