DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 88
DF36034HJV
Manufacturer Part Number
DF36034HJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034HJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 3 Exception Handling
3.2.3
IENR1 enables direct transition interrupts and external pin interrupts.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Rev. 4.00 Mar. 15, 2006 Page 54 of 556
REJ09B0026-0400
Bit
7
6
5
4
3
2
1
0
Bit Name
IENDT
IENWP
IEN3
IEN2
IEN1
IEN0
Interrupt Enable Register 1 (IENR1)
Initial
Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
Reserved
This bit is always read as 1.
Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
Reserved
This bit is always read as 1.
IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3
pin are enabled.
IRQ2 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ2
pin are enabled.
IRQ1 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ1
pin are enabled.
IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.
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