DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 443
DF36034HJV
Manufacturer Part Number
DF36034HJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034HJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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19.3.2
LVDR (Reset by Low Voltage Detect) Circuit:
Figure 19.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 50 s (t
stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1. After that, the output
settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit
should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits
must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock ( ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below V
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
RES
Vcc
PSS-reset
signal
OVF
Internal reset
signal
Low-Voltage Detection Circuit
LVDON
Vpor
t
PWON
) until the reference voltage and the low-voltage-detection power supply have
Figure 19.2 Operational Timing of Power-On Reset Circuit
PSS counter starts
131,072 cycles
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Reset released
LVDRmin
Rev. 4.00 Mar. 15, 2006 Page 409 of 556
= 1.0 V and then rises from that
REJ09B0026-0400
Vss
Vss
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