DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 392

• Manufacturer Part Number: DF36034HJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-Q
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36034HJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Synchronous Serial Communication Unit (SSU)
16.3.6
SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of
serial data, it transfers the received serial data from SSTRSR and the data is stored. After this,
SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in this way,
continuous receive operations are possible. SSRDR is a read-only register and cannot be written to
by the CPU. SSRDR is initialized to H'00.
16.3.7
SSTDR is an 8-bit register that stores serial data for transmission. SSTDR can be read or written
to by the CPU at all times. When the SSU detects that SSTRSR is empty, it transfers the transmit
data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has
already been written to SSTDR during serial transmission, continuous serial transmission is
possible. SSTDR is initialized to H 00.
16.3.8
SSTRSR is a shift register that transmits and receives serial data. When transmit data is transferred
from SSTDR to SSTRSR, bit 0 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in
SSMR is 0 (LSB-first transfer) and bit 7 in SSTDR is transferred to bit 0 in SSTRSR while the
MLS bit in SSMR is 1 (MSB-first transfer). SSTRSR cannot be directly accessed by the CPU.
Rev. 4.00 Mar. 15, 2006 Page 358 of 556
REJ09B0026-0400
SS Receive Data Register (SSRDR)
SS Transmit Data Register (SSTDR)
SS Shift Register (SSTRSR)