DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 342
DF36034HJV
Manufacturer Part Number
DF36034HJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034HJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.8
TXCR cancels transmission of transmit pending messages in Mailboxes. By setting the TXCR bit
correspondent to TXPR, TXPR is cleared to 0. If the transmission has been canceled successfully,
the corresponding bits in both TXPR and TXCR are cleared to 0 and then the corresponding bit in
ABACK is set. Writing 0 to the bit in TXCR is ignored.
15.3.9
TXACK is a status flag that indicates the successful transmit completion of Mailbox transmit
messages.
Rev. 4.00 Mar. 15, 2006 Page 308 of 556
REJ09B0026-0400
Bit
7 to 4
3
2
1
0
Bit
7 to 4
3
2
1
Bit Name
—
MB3
MB2
MB1
—
Bit Name
—
MB3
MB2
MB1
Transmit Pending Cancel Register (TXCR)
Transmit Acknowledge Register (TXACK)
Initial
Value
All 0
0
0
0
0
Initial
Value
All 0
0
0
0
R/W
—
R/W
R/W
R/W
—
R/W
—
R/(W)*
R/(W)*
R/(W)*
Description
Reserved
These bits are always read as 0.
[Setting condition]
The corresponding bit of a mailbox is set to 1
[Clearing condition]
When the corresponding bit in TXPR is cleared (the
transmit message is canceled successfully)
Note: Writing 1 to these bits is enabled only when the
Reserved
This bit is always read as 0. This bit is relevant to the
receive-only Mailbox, and its value cannot be changed.
Description
Reserved
These bits are always read as 0.
[Setting condition]
When transmission of the message in the corresponding
Mailbox has completed successfully
[Clearing condition]
When 1 is written to these bits
TXPR bit corresponding to Mailbox is set to 1.
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