DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 322
DF36034HJV
Manufacturer Part Number
DF36034HJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034HJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 14 Serial Communication Interface 3 (SCI3)
generated at this time. All other SCI3 operations are the same as those in asynchronous mode.
Figure 14.18 shows an example of SCI3 operation for multiprocessor format reception.
Rev. 4.00 Mar. 15, 2006 Page 288 of 556
REJ09B0026-0400
Yes
No
No
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
Read OER and FER flags in SSR
Read OER and FER flags in SSR
Set MPIE bit in SCR3 to 1
Read receive data in RDR
Read receive data in RDR
Clear RE bit in SCR3 to 0
Read RDRF flag in SSR
Read RDRF flag in SSR
All data received?
This station’s ID?
Start reception
FER+OER = 1
FER+OER = 1
RDRF = 1
RDRF = 1
<End>
Yes
Yes
Yes
No
No
No
[A]
Yes
No
Yes
[3]
[1]
[2]
Error processing
(Continued on
[4]
next page)
[5]
[1]
[2]
[3]
[4]
[5]
Set the MPIE bit in SCR3 to 1.
Read OER and FER in SSR to check for
errors. Receive error processing is performed
in cases where a receive error occurs.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again.
When data is read from RDR, the RDRF flag
is automatically cleared to 0.
Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
If a receive error occurs, read the OER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the OER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RxD pin value.
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