M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 81

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 8.4 MCD Register
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
0 -
Main Clock Division Register
b7
. v
NOTES:
u
1
p
0
0
b6
1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the microcomputer enters stop mode or low-power consumption mode, the MCD4 to MCD0 bits
3. Bit combinations cannot be set not listed above.
, 1
0
are set to "01000
The MCD4 to MCD0 bits are not set to "01000
(X
2
b5
0
IN
0
-X
b4
5
OUT
b3
Page 60
stopped) in on-chip oscillator mode.
b2
b1
2
".
b0
f o
(b7 - b5)
MCD0
MCD1
MCD2
MCD3
Symbol
MCD4
3
3
Bit
0
Symbol
MCD
Main Clock Division
Select Bit
Reserved Bit
(1)
Bit Name
(2)
Address
000C
2
" even if the CM05 bit in the CM0 register is set to "1"
16
b4 b3 b2 b1 b0
1 0 0 1 0: Divide-by-1(no division)
0 0 0 1 0: Divide-by-2 mode
0 0 0 1 1: Divide-by-3 mode
0 0 1 0 0: Divide-by-4 mode
0 0 1 1 0: Divide-by-6 mode
0 1 0 0 0: Divide-by-8 mode
0 1 0 1 0: Divide-by-10 mode
0 1 1 0 0: Divide-by-12 mode
0 1 1 1 0: Divide-by-14 mode
0 0 0 0 0: Divide-by-16 mode
When read,
its content is indeterminate
mode
After Reset
XXX0 1000
Function
2
8. Clock Generation Circuit
(Note 3)
RW
RW
RW
RW
RW
RW
RO