M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 110

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
10.6 Interrupt Request Acknowledgement
e
E
3
. v
J
2
Table 10.3 Interrupt Priority Levels
0
C
Software interrupts and special interrupts occur when conditions to generate an interrupt are met.
The peripheral function interrupts are acknowledged when all conditions below are met.
• I flag
• IR bit
• ILVL2 to ILVL0 bits
The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the
FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.
10.6.1 I Flag and IPL
10.6.2 Interrupt Control Register and RLVL Register
1
9
0 .
8 /
B
The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable
interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically
set to "0" after reset.
IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7.
If a requested interrupt has higher priority level than indicated by IPL, the interrupt is acknowledged.
Table 10.3 lists interrupt priority levels associated with IPL.
IPL2
The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 10.3
and 10.4 show the interrupt control register. Figure 10.5 shows the RLVL register.
0
0
0
0
0
0
0
1
1
1
1
2
7
G
N
1
o
o r
0 -
. v
u
1
0
p
0
, 1
0
2
IPL1
0
0
0
1
1
0
0
1
1
0
5
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IPL0
1
0
1
0
1
0
1
0
= "1"
= "1"
> IPL
f o
3
3
0
Level 1 and above
Level 2 and above
Level 3 and above
Level 4 and above
Level 5 and above
Level 6 and above
Level 7 and above
All maskable interrupts are disabled
Interrupt Priority Levels
10. Interrupts