M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 123

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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2
Figure 10.13 Intelligent I/O Interrupt
0
C
10.11 Intelligent I/O Interrupt
1
9
0 .
8 /
B
Interrupt Request
Interrupt Request
Interrupt Request
0
0
0
The intelligent I/O interrupt is assigned to software interrupt numbers 44 to 48.
When using the intelligent I/O interrupt, set the IRLT bit in the IIOiIE register (i = 0 to 4) to "1" (interrupt
request for interrupt used).
Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is gen-
erated with each intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1"
(interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled),
the IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested).
After the IR bit setting changes "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is
set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1".
Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each
bit to "0" by program. If these bit settings are left "1", all generated interrupt requests are ignored.
Figure 10.13 shows a block diagram of the intelligent I/O interrupt. Figure 10.14 shows the IIOiIR
register. Figure 10.15 shows the IIOiIE register.
2
7
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1
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1
0
0
p
, 1
0
2
0
0
(1)
(1)
(1)
5
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IIOiIR Register
IIOiIE Register
Bit 1
Bit 2
Bit 7
Bit 1
Bit 2
Bit 7
f o
3
(2)
(3)
3
0
IRLT Bit in the
IIOiIE Register
0
1
0
1
0
1
NOTES:
i= 0 to 4
1. See Figures 10.14 and 10.15 about bits 7 to 1 in the
2. Bits 7 to 1 in the IIOiIR register are not set to "0"
3. Do not change the IRLT bit and the interrupt enable bit
IIOiIR register and bits 1 to 7 in the IIOiIE register.
automatically even if an interrupt request is
generated. Set to "0" by program.
in the IIOiIE register simultaneously.
Intelligent I/O Interrupt i Request
10. Interrupts