M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 208

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

R
R
M
e
E
3
. v
J
2
Figure 16.15 Receive Operation
Table 16.11 Bit Rate
0
C
1
16.2.1 Bit Rate
9
B
0 .
8 /
B
t i
b (
In UART mode, bit rate is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4)
register and again divided by 16. Table 16.11 lists an example of bit rate setting.
1
1
2
3
3
5
0
0
0
R
p
1
2
4
9
4
9
8
1
8
1
2
) s
a
2
4
8
6
4
2
8
2
4
2
7
G
8-bit Data Receive Timing (with no parity and 1 stop bit)
N
UiBRG register
setting output
RxDi
Transfer Clock
RI bit in the UiC1
register
RTSi
IR bit in the SiRIC
register
e t
RE bit in the
UiC1 register
0
0
0
0
0
0
0
5
0
0
1
o
o r
0
0
0
0
0
0
0
0
0
0
0 -
. v
u
1
0
0
p
S
U
C
, 1
0
o
B i
o
f o
8 f
8 f
8 f
u
1 f
1 f
1 f
1 f
1 f
1 f
1 f
2
u
R
c r
0
t n
G
e
0
5
i=0 to 4
NOTE:
Page 187
"1"
"0"
"1"
"0"
"H"
"L"
"1"
"0"
S
1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled),
f o
t e
P
Start receiving when the transfer clock is
generated on the falling edge of the start bit
the STPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set
to "1" (RTS function selected).
U
n i t
r e
1
1
B i
3
0
5
2
0
6
5
3
2
1
g
p i
1
R
3
1
5
3
8
1
4
5
9
V
h
: G
1 (
6 (
3 (
1 (
6 (
4 (
3 (
2 (
1 (
1 (
r e
a
u l
F
l a
7
3
9
7
4
3
2
9
3
n
f o
e
1
) h
) h
) h
) h
) h
) h
) h
) h
) h
) h
F
6
3
M
u
Start bit
3
n
H
0
A
t c
z
c
o i
u t
Verify if an "L"
signal is applied
n
l a
b (
C
B
p
o l
t i
) s
3
3
5
1
1
2
c
R
1
2
4
9
4
1
8
0
9
8
: k
2
4
8
6
4
2
4
0
a
Set to "0" by an interrupt request acknowledgement or by program
2
5
0
e t
0
0
1
9
5
6
0
3
7
2
4
8
5
3
0
2
0
1
1
S
D
f o
t e
0
P
U
n i t
r e
1
1
1
Capture a received data
B i
2
5
7
3
5
0
7
5
4
3
Data is transferred from the UARTi receive
register to the UiRB register
p i
g
8
R
7
5
7
8
5
3
7
1
8
h
V
: G
1 (
Change to "L" by reading the UiRB register
2 (
9 (
4 (
2 (
9 (
6 (
4 (
3 (
2 (
r e
a
u l
C
6
6
6
6
7
6
3
F
6
l a
n
2
e
) h
) h
) h
) h
) h
) h
) h
) h
) h
) h
F
4
M
u
D
n
H
A
1
t c
z
c
o i
u t
n
l a
b (
D
C
B
p
7
o l
) s
t i
1
2
3
3
5
1
c
R
1
2
4
9
8
1
8
1
4
9
: k
a
2
4
8
6
4
8
2
4
7
2
e t
0
0
0
1
4
5
6
2
2
3
2
4
8
5
3
6
0
2
4
1
Stop bit
S
f o
P
t e
r e
U
n i t
2
2
1
1
1
B i
p i
0
0
3
6
0
5
0
6
5
3
g
7
7
R
8
3
1
3
8
3
1
8
h
V
r e
: G
(
(
8 (
6 (
3 (
6 (
4 (
3 (
3 (
2 (
16. Serial I/O (UART)
a
C
C
l a
u l
A
F
F
F
7
3
7
4
3
6
n
3
e
) h
) h
) h
) h
) h
) h
) h
) h
) h
) h
2
F
M
u
n
H
A
t c
z
c
o i
u t
n
l a
b (
C
B
p
o l
) s
1
2
3
3
5
t i
1
2
c
1
4
9
4
8
1
8
1
9
R
: k
2
4
8
6
3
9
2
4
2
2
a
0
8
0
0
1
8
5
6
8
3
e t
2
4
8
5
8
6
0
2
2
1