MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 587

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

valid bit. These registers’ contents are compared with the processor’s program counter register when TDR
is configured appropriately.
The PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and
through the BDM port using the WRITE_DREG command using values shown in
Command Set Descriptions”.
Figure 26-12
via the BDM port using the WRITE_DREG command. PBMR only masks PBR0.
Freescale Semiconductor
Address
Address
Field
Field
31–0
31–1
V
0
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0
DRc: 0x08 (PBR0)
DRc: 0x18 (PBR1)
PC breakpoint address. The address to be compared with the PC as a breakpoint trigger. Because all instruction
sizes are multiples of 2 bytes, bit 0 of the address should always be zero.
PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint trigger.
Valid bit. This bit must be set for the PC breakpoint to occur at the address specified in the Address field.
0 PBR is disabled.
1 PBR is enabled.
W
W
R
R
shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and
0x1A (PBR2)
0x1C (PBR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Version 1 ColdFire core devices implement a 24-bit, 16 MB address map.
When programming these registers with a 32-bit address, the upper byte
must be zero-filled.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 26-11. Program Counter Breakpoint Register n (PBRn, n = 1,2,3)
Figure 26-10. Program Counter Breakpoint Register 0 (PBR0)
Table 26-15. PBR0 Field Descriptions
Table 26-16. PBRn Field Descriptions
NOTE
Description
Description
Address
Address
Version 1 ColdFire Debug (CF1_DEBUG)
Access: Supervisor write-only
Access: Supervisor write-only
8
8
7
7
Section 26.4.1.4, “BDM
6
6
5
5
BDM write-only
BDM write-only
4
4
3
3
2
2
1
1
V
0
0
26-23