MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 147

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

At reset, all bits in the RGPIO_DIR are cleared.
5.3.2
The RGPIO_DATA register specifies the write data for a properly-enabled RGPIO output pin or the
sampled read data value for a properly-enabled input pin. An attempted read of the RGPIO_DATA register
returns undefined data for disabled pins, since the data value is dependent on the device-level pin muxing
and pad implementation. The RGPIO_DATA register is read/write. At reset, all bits in the RGPIO_DATA
registers are cleared.
To set bits in a RGPIO_DATA register, directly set the RGPIO_DATA bits or set the corresponding bits in
the RGPIO_SET register. To clear bits in the RGPIO_DATA register, directly clear the RGPIO_DATA
bits, or clear the corresponding bits in the RGPIO_CLR register. Setting a bit in the RGPIO_TOG register
inverts (toggles) the state of the corresponding bit in the RGPIO_DATA register.
Freescale Semiconductor
Offset: RGPIO_Base + 0x0 (RGPIO_DIR)
Field
Offset: RGPIO_Base + 0x2 (RGPIO_DATA)
15–0
Reset
DIR
Reset
W
W
R
R
RGPIO_Base + 0x8
RGPIO_Base + 0xC
RGPIO_Base + 0x6
RGPIO_Base + 0xA
RGPIO_Base + 0xE
RGPIO data direction.
0 A properly-enabled RGPIO pin is configured as an input
1 A properly-enabled RGPIO pin is configured as an output
15
15
0
0
RGPIO Data (RGPIO_DATA)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
14
14
0
0
13
13
0
0
Figure 5-3. RGPIO Data Direction Register (RGPIO_DIR)
12
12
0
0
Figure 5-4. RGPIO Data Register (RGPIO_DATA)
Table 5-5. RGPIO_DIR Field Descriptions
11
11
0
0
10
10
0
0
0
0
9
9
Description
8
0
8
0
DATA
DIR
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
Rapid GPIO (RGPIO)
Access: Read/write
Access: Read/write
Read/Indirect Write
Read/Indirect Write
Read/Indirect Write
0
0
2
2
0
0
1
1
Read-only
Read-only
0
0
0
0
5-7