MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 582

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Version 1 ColdFire Debug (CF1_DEBUG)
development system. BAAR is loaded any time AATR is written and is initialized to a value of 0x05,
setting supervisor data as the default address space. The upper 24 bits of this register are reserved for future
use and any attempted write of these bits is ignored.
26.3.6
AATR defines address attributes and a mask to be matched in the trigger. The register value is compared
with address attribute signals from the processor’s high-speed local bus, as defined by the setting of the
trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06
using the WDEBUG instruction and through the BDM port using the WRITE_DREG command.
26-18
Field
31–8
6–5
4–3
2–0
TM
SZ
TT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
7
DRc: 0x06 (AATR)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
DRc: 0x05 (BAAR)
W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM SZM
R
W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
R
Reserved for future use by the debug module, must be cleared.
Read/Write.
0 Write
1 Read
Size.
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. See the TT definition in the AATR description,
(AATR)”.
Transfer modifier. See the TM definition in the AATR description,
(AATR)”.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address Attribute Trigger Register (AATR)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 26-8. Address Attribute Trigger Register (AATR)
Figure 26-7. BDM Address Attribute Register (BAAR)
Table 26-12. BAAR Field Descriptions
Description
0
14
0
Section 26.3.6, “Address Attribute Trigger Register
13
0
Section 26.3.6, “Address Attribute Trigger Register
12
0
TTM
11
0
10
0
TMM
0
9
9
8
0
Access: Supervisor write-only
8
Access: Supervisor write-only
R
0
7
7
0
6
6
Freescale Semiconductor
SZ
SZ
5
0
5
4
BDM write-only
0
4
TT
TT
BDM write-only
3
0
3
2
1
2
TM
1
TM
0
1
0
1
0