MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 340

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Inter-Integrated Circuit (IIC)
15.1.3
Figure 15-1
15.2
This section describes each user-accessible pin signal.
15.2.1
The bidirectional SCL is the serial clock line of the IIC system.
15-2
•
•
•
Run mode — This is the basic mode of operation. To conserve power in this mode, disable the
module.
Wait mode — The module will continue to operate while the MCU is in wait mode and can
provide a wake-up interrupt.
Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP
instruction does not affect IIC register states. Stop2 will reset the register contents.
External Signal Description
Block Diagram
SCL — Serial Clock Line
is a block diagram of the IIC.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
CTRL_REG
INPUT FILTER
ADDR_DECODE
CONTROL
ADDRESS
CLOCK
SYNC
Figure 15-1. IIC Functional Block Diagram
FREQ_REG
SCL
ARBITRATION
TIMEOUTS
ACK/NACK
CONTROL
ADDR_REG
START
STOP
SDA
STATUS_REG
INTERRUPT
REGISTER
COMPARE
ADDRESS
IN/OUT
SHIFT
DATA
DATA_MUX
DATA_REG
DATA BUS
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