MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 298

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16-Bit Serial Peripheral Interface (SPI16)
For FIFO management there are two other important flags that are used to help make the operation more
efficient when transfering large amounts of data. These are the Receive FIFO Nearly Full Flag
(RNFULLF) and the Transmit FIFO Nearly Empty Flag (TNEAREF). Both these flags provide a
“watermark” feature of the FIFOs to allow continuous transmissions of data when running at high speed.
The RNFULLF flag can generate an interrupt if the RNFULLIEN bit in the SPIxC3 Register is set which
allows the CPU to start emptying the Receive FIFO without delaying the reception of subsequent bytes.
The user can also determine if all data in Receive FIFO has been read by monitoring the RFIFOEF flag.
The TNEAREF flag can generate an interrupt if the TNEARIEN bit n the SPIxC3 Register is set which
allows the CPU to start filling the Transmit FIFO before it is empty and thus provide a mechanism to have
no breaks in SPI transmission.
Figure 13-7
13.3.5
13-12
Reset
Reset
Reset
W
W
W
R
R
R
SPRF
SPRF
Bit 15
SPI Data Registers (SPIxDH:SPIxDL)
and
0
0
0
7
7
7
SPIxS and both TX and RX fifos gets reset due to change in SPIMODE,
FIFOMODE or SPE. PoR values of SPIxS are show in
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 13-8
Figure 13-7. Reset values of SPIxS after PoR with FIFOMODE = 0
Figure 13-8. Reset values of SPIxS after PoR with FIFOMODE = 1
SPMF
SPMF
14
0
0
0
6
6
6
shows the reset values due to change of modes after PoR.
Figure 13-9. SPI Data Register High (SPIxDH)
SPTEF
SPTEF
13
1
1
0
5
5
5
MODF
MODF
NOTE
12
0
0
0
4
4
4
RNFULLF
RNFULLF
11
3
0
3
0
3
0
Figure
TNEAREF
TNEAREF
10
0
1
0
2
2
2
13-7.
TXFULLF
TXFULLF
Freescale Semiconductor
0
0
9
0
1
1
1
RFIFOEF
RFIFOEF
Bit 8
0
1
0
0
0
0