MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 268

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Internal Clock Source (ICS)
11.4.1.2
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock source.The FLL loop locks the frequency to the FLL factor times the external
reference frequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications,
and the external reference clock is enabled.
11.4.1.3
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop locks the FLL frequency to the FLL
factor times the internal reference frequency. The ICSLCLK will be available for BDC communications,
and the internal reference clock is enabled.
11.4.1.4
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal
reference clock is enabled.
11.4.1.5
The FLL bypassed external (FBE) mode is entered when all the following conditions occur:
11-14
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CLKS bits are written to 00.
IREFS bit is written to 0.
RDIV bits are written to divide external reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
CLKS bits are written to 01.
IREFS bit is written to 1.
BDM mode is active or LP bit is written to 0.
CLKS bits are written to 01.
IREFS bit is written to 1.
BDM mode is not active and LP bit is written to 1.
CLKS bits are written to 10.
IREFS bit is written to 0.
RDIV bits are written to divide external reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
BDM mode is active or LP bit is written to 0.
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
FLL Bypassed Internal Low Power (FBILP)
FLL Bypassed External (FBE)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 1.11
Freescale Semiconductor