DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 461

• Manufacturer Part Number: DF2210CUNP24V
• Description: MCU 16BIT FLASH 3V 32K 64-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2210CUNP24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the 8th
pulse of the basic clock as shown in Figure 12.6. Thus, the reception margin in asynchronous
mode is given by formula (1) below.
M = | (0.5 –
Where M: Reception margin
Assuming values of F (absolute value of clock rate deviation) = 0, D (clock duty) = 0.5, and N
(ratio of bit rate to clock) = 16 in formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Note: * In this example the value of the ABCS bit in SEMRA_0 is 0. When ABCS is set to 1, the basic clock frequency
N: Ratio of bit rate to clock (N = 16 if ABCS = 0, N = 8 if ABCS = 1)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
is eight times the bit rate and the receive data is sampled at the fourth rising edge of the basic clock.
2N
Figure 12.6 Receive Data Sampling Timing in Asynchronous Mode
1
) – (L – 0.5) F –
0
8 clocks *
Start bit
16 clocks *
| D – 0.5 |
7
N
(1+ F) | × 100 [%]
15 0
Rev.7.00 Dec. 24, 2008 Page 405 of 698
D0
... Formula (1)
7
REJ09B0074-0700
15 0
D1