DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 217

• Manufacturer Part Number: DF2210CUNP24V
• Description: MCU 16BIT FLASH 3V 32K 64-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2210CUNP24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.3
7.3.1
• Short Address Mode
• Full Address Mode
7.3.2
• Short Address Mode
• Full Address Mode:
MAR is a 32-bit readable/writable register that specifies the transfer source address or
destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and
cannot be modified. Whether MAR functions as the source address register or as the
destination address register can be selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated. For details, see section 7.3.4, DMA Control
Register (DMACR). MAR is not initialized by a reset or in standby mode.
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address
register, and MARB as the destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are
reserved: they are always read as 0, and cannot be modified. MAR is incremented or
decremented each time a byte or word transfer is executed, so that the source or destination
memory address can be updated automatically. For details, see section 7.3.4, DMA Control
Register (DMACR). MAR is not initialized by a reset or in standby mode.
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer
source address or destination address. The upper 8 bits of the transfer address are automatically
set to H'FF. Whether IOAR functions as the source address register or as the destination
address register can be selected by means of the DTDIR bit in DMACR.
IOAR is not incremented or decremented each time a transfer is executed, so that the address
specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode.
IOAR is not used in full address mode transfer.
Memory Address Registers (MAR)
I/O Address Register (IOAR)
Register Descriptions
Rev.7.00 Dec. 24, 2008 Page 161 of 698
REJ09B0074-0700