HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet - Page 207

• Manufacturer Part Number: HD64F3672FPIV
• Description: MCU 3/5V 16K I-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPIV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4.4
Figure 13.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Serial
data
RDRF
FER
LSI
operation
User
processing
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Figure 13.7 Example SCI3 Operation in Reception in Asynchronous Mode
Serial Data Reception
1
Start
bit
0
D0
D1
Receive
1 frame
data
(8-Bit Data, Parity, One Stop Bit)
D7
Parity
0/1
bit
RXI request
Stop
bit
1
Start
bit
0
D0
RDRF
cleared to 0
RDR data read
Section 13 Serial Communication Interface 3 (SCI3)
1 frame
D1
Receive
data
Rev.4.00 Nov. 02, 2005 Page 181 of 304
D7
Parity
0/1
bit
Stop
bit
0
0 stop bit
detected
Mark state
(idle state)
1
REJ09B0143-0400
ERI request in
response to
framing error
Framing error
processing