HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet - Page 180

MCU 3/5V 16K I-TEMP PB-FREE 64-L

HD64F3672FPIV

Manufacturer Part Number
HD64F3672FPIV
Description
MCU 3/5V 16K I-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3672FPIV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 11 Timer W
11.5.6
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Figure 11.21 shows the timing of the IMFA to IMFD flag setting at compare match.
Rev.4.00 Nov. 02, 2005 Page 154 of 304
REJ09B0143-0400
Timing of IMFA to IMFD Flag Setting at Compare Match
Figure 11.21 Timing of IMFA to IMFD Flag Setting at Compare Match
TCNT input
clock
TCNT
GRA to GRD
Compare
match signal
IMFA to IMFD
IRRTW
Input capture
signal
TCNT
GRA, GRB
GRC, GRD
Figure 11.20 Buffer Operation Timing (Input Capture)
N
N
M
N
N
M
N+1
N+1
N+1
N

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