MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 173

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DDRB[7:0] — Data Direction Register B Bits
Figure 13-7
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
shows the port B I/O circuit logic.
Address:
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Reset:
Read:
Write:
DDRB
Bit
0
1
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRB7
$0005
Bit 7
0
Figure 13-6. Data Direction Register D (DDRD)
PTB Bit
X
X
(1)
DDRB6
6
0
Table 13-3. Port B Pin Functions
RESET
MC68HC908JW32 Data Sheet, Rev. 6
Figure 13-7. Port B I/O Circuit
I/O Pin Mode
Input, Hi-Z
DDRB5
Output
5
0
Table 13-3
(2)
NOTE
DDRB4
DDRBx
PTBx
4
0
Read/Write
DDRB[7:0]
DDRB[7:0]
Accesses
to DDRB
summarizes the operation of the port B pins.
DDRB3
3
0
DDRB2
PTB[7:0]
Read
2
0
Pin
Accesses to PTB
DDRB1
1
0
PTB[7:0]
PTB[7:0]
Write
DDRB0
Bit 0
PTBx
(3)
0
Port B
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