ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 99

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 0 = CMPIE Compare Interrupt Enable bit
Counter register 1 High (CNTR1H)
Reset value: 0000 0000 (00h)
Counter register 1 Low (CNTR1L)
Reset value: 0000 0000 (00h)
Bits 15:12 = Reserved
Bits 11:0 = CNTR1[11:0] Counter value
CNTR1_7
This bit is read/write by software and cleared by hardware after a reset. it can be used
to mask the interrupt generated when any of the cmpfx bit is set.
0: Output Compare Interrupt Disabled.
1: Output Compare Interrupt Enabled.
This 12-bit register is read by software and cleared by hardware after a reset. The
counter CNTR1 increments continuously as soon as a counter clock is selected. To
obtain the 12-bit value, software should read the counter value in two consecutive read
operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTR1H can be incremented between the two read operations and to have an
accurate result when f
close to FFh are read.
When a counter overflow occurs, the counter restarts from the value specified in the
ATR1 register.
15
7
0
CNTR1_6
0
CNTR1_5
timer
0
=f
CPU
CNTR1_4
, special care must be taken when CNTR1L values
0
Read only
Read only
CNTR1_3
CNTR1_
11
CNTR1_2
CNTR1_
10
CNTR1_9
CNTR1_1
On-chip peripherals
CNTR1_8
CNTR1_0
8
0
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