ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 150

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
10.5.7
Note:
Note:
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Register description
I
Reset value: 0000 0000 (00h)
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral Enable bit
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I
activates the interface (only PE is set).
Bit 4 = ENGC Enable General Call bit
In accordance with the I
only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition bit. This bit is set and cleared by software. It
is also cleared by hardware when the interface is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if ITE=1).
Bit 2 = ACK Acknowledge enable bit
2
C Control register (I2CCR)
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
In master mode:
0: No start generation
1: Repeated start generation
In slave mode:
0: No start generation
1: Start generation when the bus is free
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
7
0
2
C interface, write the CR register TWICE with PE=1 as the first write only
0
2
C standard, when GCAL addressing is enabled, an I
PE
ENGC
Read / Write
START
ST7FOXF1, ST7FOXK1, ST7FOXK2
ACK
STOP
2
C slave can
ITE
0