ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 101

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 2 = OPEDGE One Pulse Edge Selection bit
Bit 1 = OPx PWMx Output Polarity bit
Bit 0 = CMPFx PWMx Compare flag
Break control register 1 (BREAKCR1)
Reset value: 0000 0000 (00h)
Bit 7 = BR1SEL Break 1 input selection bit (only available on ST7FOXK2, reserved for
ST7FOXF1/ST7FOXK1)
Bit 6 = BR1EDGE Break 1 input edge selection bit (BREDGE on ST7FOXF1/ST7FOXK1)
BR1SEL
This bit is read/write by software and cleared by hardware after a reset. This bit enables
the One Pulse feature for PWM2 and PWM3 (only available for PWM3CSR)
0: One Pulse mode disable for PWM2/3.
1: One Pulse mode enable for PWM2/3.
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if
OP_EN bit is set (only available for PWM3CSR)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
This bit is set by hardware and cleared by software by reading the PWMxCSR register.
It indicates that the upcounter value matches the Active DCRx register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
This bit is read/write by software and cleared by hardware after reset. It selects the
active Break 1 signal from external BREAK1 pin and the output of the comparator.
0: External BREAK1 pin is selected for break mode.
1: Comparator 1 output is selected for break mode.
This bit is read/write by software and cleared by hardware after reset. It selects the
active level of Break 1 signal.
0: Low level of Break 1selected as active level
1: High level of Break 1selected as active level
7
BR1EDGE
BA1
BP1EN
Read/write
PWM3
PWM2
On-chip peripherals
PWM1
PWM0
101/226
0