P89LPC9408FBD,557 NXP Semiconductors, P89LPC9408FBD,557 Datasheet - Page 35

• Manufacturer Part Number: P89LPC9408FBD,557
• Description: IC 80C51 MCU FLASH 8K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9408FBD,557

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 64-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LED, POR, PWM, WDT
• Number Of I /o: 23
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10097 - KIT FOR LCD DEMO LPC9408EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3228; 935280583557; P89LPC9408FBD

Philips Semiconductors
P89LPC9408_1
Product data sheet
7.20.10 The 9
7.20.8 Double buffering
7.20.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
7.21 I
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
Unlike the conventional UART, in double buffering mode, the TX interrupt is generated
when the double buffer is ready to receive new data.
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TX interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
The I
connected to the bus, and it has the following features:
A typical I
byte-oriented I
2
•
•
•
•
•
•
C-bus serial interface
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
th
bit (bit 8) in double buffering (modes 1, 2 and 3)
2
2
C-bus may be used for test and diagnostic purposes.
C-bus configuration is shown in
8-bit two-clock 80C51 core with 32 segment
2
C-bus interface that supports data transfers up to 400 kHz.
Rev. 01 — 16 December 2005
Figure
13. The P89LPC9408 device provides a
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
P89LPC9408
4 LCD driver, 10-bit ADC
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