P89LPC9408FBD,557 NXP Semiconductors, P89LPC9408FBD,557 Datasheet - Page 28

IC 80C51 MCU FLASH 8K 64-LQFP

P89LPC9408FBD,557

Manufacturer Part Number
P89LPC9408FBD,557
Description
IC 80C51 MCU FLASH 8K 64-LQFP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC9408FBD,557

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
64-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LED, POR, PWM, WDT
Number Of I /o
23
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC9x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
OM10097 - KIT FOR LCD DEMO LPC9408EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-3228
935280583557
P89LPC9408FBD

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P89LPC9408FBD,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
P89LPC9408_1
Product data sheet
7.16.1 Reset vector
7.17 Timers/counters 0 and 1
Remark: During a power-up sequence, the RPE selection is overridden and this pin will
always function as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as defined by the RPE bit. Only a power-up reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
Following reset, the P89LPC9408 will fetch instructions from either address 0000H or the
Boot address. The Boot address is formed by using the Boot Vector as the high byte of the
address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC9408 User manual ). Otherwise, instructions will be fetched from address 0000H.
The P89LPC9408 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
External reset pin (during power-up or if user configured via UCFG1).
Power-on detect.
Brownout detect.
Watchdog timer.
Software reset.
UART break character detect reset.
During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
For any other reset, previously set flag bits that have not been cleared will remain set.
8-bit two-clock 80C51 core with 32 segment
Rev. 01 — 16 December 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
P89LPC9408
4 LCD driver, 10-bit ADC
28 of 69

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