AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 743

• Manufacturer Part Number: AT32UC3A0512-ALTTA
• Description: IC MCU AVR32 512K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0512-ALTTA

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

36.4
Table 36-1.
36.5
36.5.1
36.6
36.6.1
32058J–AVR32–04/11
Name
TCK
TMS
TDI
TDO
I/O Lines Description
Product Dependencies
Functional description
I/O Lines
JTAG interface
I/O Lines Description
Description
Test Mode Select, sampled on rising TCK
Test Clock Input. Fully asynchronous to system clock frequency.
Test Data In, sampled on rising TCK.
Test Data Out, driven on falling TCK.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The JTAG interface pins are multiplexed with IO lines. When the JTAG is used the associated
pins must be enabled. To enable the JTAG pins TCK must be zero while RESET_N has a zero
to one transition. To disable the JTAG pins TCK must be one while RESET_N has a zero to one
transition.
While using the JTAG lines all normal peripheral activity on these lines are disabled. The user
must make sure that no external peripheral is blocking the JTAG lines while debugging.
The JTAG interface is accessed through the dedicated JTAG pins shown in
743. The TMS control line navigates the TAP controller, as shown in
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied
at the start of a JTAG session to bring the TAP Controller into a defined state before applying
JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the Run-
Test/Idle state, which is the starting point for JTAG operations.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in
of AVR32-specific private JTAG instructions described in
a specific data register for the Shift-DR path, as described for each instruction.
Section
Section
36.9. Each instruction selects
Figure 36-2 on page
36.8, as well as a number
AT32UC3A
Table 36-1 on page
Type
Input
Input
Input
Output
744.
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