AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 517
AT32UC3A0512-ALTTA
Manufacturer Part Number
AT32UC3A0512-ALTTA
Description
IC MCU AVR32 512K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.ATEVK1104.pdf
(826 pages)
Specifications of AT32UC3A0512-ALTTA
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 30-18. Example of an IN Endpoint with 2 Data Banks
30.7.2.12.2 Detailed Description
32058J–AVR32–04/11
TXINI
FIFOCON
SW
write data to CPU
The data is written by the firmware, following the next flow:
If the endpoint uses several banks, the current one can be written by the firmware while the pre-
vious one is being read by the host. Then, when the firmware clears FIFOCON, the following
bank may already be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The KILLBK bit is used to kill the last written
bank. The best way to manage this abort is to apply the algorithm represented on
•when the bank is empty, TXINI and FIFOCON are set, what triggers an EPXINT interrupt if
•the firmware acknowledges the interrupt by clearing TXINI;
•the firmware writes the data into the current bank by using the USB Pipe/Endpoint X FIFO
•the firmware allows the controller to send the bank and switches to the next bank (if any) by
BANK 0
TXINE = 1;
Data register (USB_FIFOX_DATA), until all the data frame is written or the bank is full (in
which case RWALL is cleared by hardware and BYCT reaches the endpoint size);
clearing FIFOCON.
SW
IN
SW
write data to CPU
BANK 1
(bank 0)
DATA
SW
HW
ACK
SW
write data to CPU
IN
BANK0
(bank 1)
DATA
AT32UC3A
ACK
Figure
30-19.
517
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