AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 408
AT32UC3A0512-ALTTA
Manufacturer Part Number
AT32UC3A0512-ALTTA
Description
IC MCU AVR32 512K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.ATEVK1104.pdf
(826 pages)
Specifications of AT32UC3A0512-ALTTA
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
• Data Bus Width (DBW)
• BAT: Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
1: Byte write access type:
0: Byte select access type:
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal.
Table 27-9.
• WRITE_MODE
1: The write operation is controlled by the NWE signal.
0: The write operation is controlled by the NCS signal.
• READ_MODE:
1: The read operation is controlled by the NRD signal.
32058J–AVR32–04/11
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
cycle is resumed from the point where it was stopped.
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
– Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.
– Read operation is controlled using NCS and NRD.
– Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
– Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
0
0
1
1
0
0
1
1
EXNW_MODE
EXNW_MODE
DBW
0
1
0
1
0
1
0
1
32-bit bus
Reserved
Data Bus Width
8-bit bus
16-bit bus
NWAIT Mode
Disabled
Reserved
Frozen Mode
Ready Mode
AT32UC3A
408
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