AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 25

• Manufacturer Part Number: AT32UC3A0512-ALTTA
• Description: IC MCU AVR32 512K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0512-ALTTA

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.3
9.3.1
9.3.2
32058J–AVR32–04/11
Programming Model
Register file configuration
Status register configuration
The AVR32UC register file is shown below.
Figure 9-3.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
page 25
code flags and the R, T and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 9-4.
Application
Bit 31
Bit 31
SP_APP
0
FINTPC
INT0PC
INT1PC
-
SM PC
R12
R11
R10
SR
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LC
1
0
-
Bit 0
and
0
-
Supe rv isor
Bit 31
Figure 9-5 on page
The AVR32UC Register File
The Status Register High Halfword
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
0
-
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
DM
0
D
0
INT0
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
-
Bit 0
M2
0
26. The lower word contains the C, Z, N, V and Q condition
M1
INT1
Bit 31
0
SP_SYS
FINTPC
INT0PC
INT1PC
SM PC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
M0
1
Bit 0
E M
1
INT2
Bit 31
I3M
0
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
I2M
FE
0
Bit 0
I1M
0
INT3
Bit 31
I0M
SP_SYS
FINTPC
0
INT0PC
INT1PC
SM PC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 16
GM
1
Bit 0
Bit name
Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
Exception Mask
Exce ption
Bit 31
SP_SYS
AT32UC3A
FINTPC
INT0PC
INT1PC
SM PC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
Figure 9-4 on
NMI
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
25