AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 451

• Manufacturer Part Number: AT32UC3A0512-ALTTA
• Description: IC MCU AVR32 512K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0512-ALTTA

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

29.6
29.6.1
29.6.1.1
29.6.1.2
Figure 29-2. Receive Buffer List
32058J–AVR32–04/11
Programming Interface
Initialization
Configuration
Receive Buffer List
Receive Buffer Queue Pointer
(MAC Register)
Initialization of the MACB configuration (e.g. frequency ratios) must be done while the transmit
and receive circuits are disabled. See the description of the network control register and network
configuration register later in this document.
Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed
in another data structure that also resides in main memory. This data structure (receive buffer
queue) is a sequence of descriptor entries as defined in
page
To create the list of buffers:
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and
3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit
4. Write address of receive buffer descriptor entry to MACB register receive_buffer queue
5. The receive circuits can then be enabled by writing to the address recognition registers
create n entries in this list. Mark all entries in this list as owned by MACB, i.e., bit 0 of
word 0 set to 0.
(bit 1 in word 0 set to 1).
pointer.
and then to the network control register.
440. It points to this data structure.
Receive Buffer Descriptor List
(In memory)
”Receive Buffer Descriptor Entry” on
Receive Buffer 1
Receive Buffer 0
Receive Buffer N
(In memory)
AT32UC3A
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