AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 199
AT91SAM7SE32-AU
Manufacturer Part Number
AT91SAM7SE32-AU
Description
MCU ARM 32K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7SE32-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
88
Ram Memory Size
8KB
Cpu Speed
48MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
88
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE32-AU
Manufacturer:
ATMEL
Quantity:
624
Part Number:
AT91SAM7SE32-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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• DBW: Data Bus Width
• DRP: Data Read Protocol
0: Standard Read Protocol is used.
1: Early Read Protocol is used.
• ACSS: Address to Chip Select Setup
• RWSETUP: Read and Write Signal Setup Time
See definition and description below.
• RWHOLD: Read and Write Signal Hold Time
See definition and description below
Notes:
6222B–ATARM–26-Mar-07
0
0
0
0
1
1
1
1
1. For a visual description, please refer to
2. In Standard Read Protocol.
3. In Early Read Protocol. (It is not possible to use the parameters RWSETUP or RWHOLD in this mode.)
4. When the ECC Controller is used, RWHOLD must be programmed to 1 at least.
RWSETUP
22-46
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
and
(1)
Figure 22-47 on page
ACSS
DBW
0
1
0
1
0
1
0
1
NRD Setup
½ cycle
0 cycles
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
0
1
0
1
0
1
0
1
.
(2)
(3)
or
200.
”Setup and Hold Cycles” on page 176
NWR Setup
½ cycle
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
Data Bus Width
Reserved
16-bit
8-bit
Reserved
Chip Select Waveform
Standard, asserted at the beginning of the access and deasserted at the end.
One cycle less at the beginning and the end of the access.
Two cycles less at the beginning and the end of the access.
Three cycles less at the beginning and the end of the access.
AT91SAM7SE512/256/32 Preliminary
0
0
0
0
1
1
1
1
RWHOLD
0
0
1
1
0
0
1
1
(1) (4)
and the diagrams in
0
1
0
1
0
1
0
1
NRD Hold
0
1 cycles
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
Figure 22-45
NWR Hold
½ cycle
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
and
Figure
199
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