AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 416
AT91SAM7SE32-AU
Manufacturer Part Number
AT91SAM7SE32-AU
Description
MCU ARM 32K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7SE32-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
88
Ram Memory Size
8KB
Cpu Speed
48MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
88
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE32-AU
Manufacturer:
ATMEL
Quantity:
624
Part Number:
AT91SAM7SE32-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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34.6.1.1
416
AT91SAM7SE512/256/32 Preliminary
Baud Rate in Asynchronous Mode
If the external SCK clock is selected, the duration of the low and high levels of the signal pro-
vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the
signal provided on SCK must be at least 4.5 times lower than MCK.
Figure 34-3. Baud Rate Generator
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possi-
ble clock and that OVER is programmed at 1.
SCK
Reserved
MCK/DIV
Baudrate
MCK
USCLKS
=
0
1
2
3
--------------------------------------------
(
8 2 Over
SelectedClock
(
–
16-bit Counter
)CD
CD
)
USCLKS = 3
0
SYNC
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
6222B–ATARM–26-Mar-07
0
1
SYNC
SCK
Baud Rate
Sampling
Clock
Clock
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