AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 659

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

31.2.1.8
31.2.1.9
31.2.1.10
31.2.1.11
32059J–12/2010
GPIO
OCD
Processor and Architecture
TWI
1. The TWI RXRDY flag in SR register is not reset when a software reset is performed
2. TWI in master mode will continue to read data
3. TWI slave behaves improperly if master acknowledges the last transmitted data byte
1. PA29 (TWI SDA) and PA30 (TWI SCL) GPIO VIH (input high voltage) is 3.6V max
1. The auxiliary trace does not work for CPU/HSB speed higher than 50MHz.
1. LDM instruction with PC in the register list and without ++ increments Rp
2. RETE instruction does not clear SREG[L] from interrupts
Disable and then enable the peripheral after the transfer error.
The TWI RXRDY flag in SR register is not reset when a software reset is performed.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
TWI in master mode will continue to read data on the line even if the shift register and the
RHR register are full. This will generate an overrun error.
Fix/workaround
To prevent this, read the RHR register as soon as a new RX data is ready .
before a STOP condition
In I2C slave transmitter mode, if the master acknowledges the last data byte before a STOP
condition (what the master is not supposed to do), the following TWI slave receiver mode
frame may contain an inappropriate clock stretch. This clock stretch can only be stopped by
resetting the TWI.
Fix/Workaround
If the TWI is used as a slave transmitter with a master that acknowledges the last data byte
before a STOP condition, it is necessary to reset the TWI beforeentering slave receiver
mode.
instead of 5V tolerant
The following GPIOs are not 5V tolerant : PA29 and PA30.
Fix/Workaround
None.
The auxiliary trace does not work for CPU/HSB speed higher than 50MHz.
Workaround:
Do not use the auxiliary trace for CPU/HSB speed higher than 50MHz.
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
The RETE instruction clears SREG[L] as expected from exceptions.
Fix/Workaround
When using the STCOND instruction, clear SREG[L] in the stacked value of SR before
returning from interrupts with RETE.
AT32UC3B
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