AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 121

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. Flash Controller (FLASHC)
14.1
14.2
14.3
14.3.1
14.3.2
32059J–12/2010
Features
Overview
Product dependencies
Power Manager
Interrupt Controller
Rev: 2.1.2.4
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The flash controller (FLASHC) interfaces a flash block with the 32-bit internal High-Speed Bus
(HSB). Performance for uncached systems with high clock-frequency and one wait state is
increased by placing words with sequential addresses in alternating flash subblocks. Having one
read interface per subblock allows them to be read in parallel. While data from one flash sub-
block is being output on the bus, the sequential address is being read from the other flash
subblock and will be ready in the next clock cycle.
The controller also manages the programming, erasing, locking and unlocking sequences with
dedicated commands.
The FLASHC has two bus clocks connected: One High speed bus clock (CLK_FLASHC_HSB)
and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are generated by the Power
manager. Bot h clocks are turned on by default, but the user has t o ensure that
CLK_FLASHC_HSB is not turned off before reading the flash or writing the pagebuffer and that
CLK_FLASHC_PB is not turned off before accessing the FLASHC configuration and control
registers.
The FLASHC interrupt lines are connected to internal sources of the interrupt controller. Using
FLASHC interrupts requires the interrupt controller to be programmed first.
Controls flash block with dual read ports allowing staggered reads.
Supports 0 and 1 wait state bus access.
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
32-bit HSB interface for reads from flash array and writes to page buffer.
32-bit PB interface for issuing commands to and configuration of the controller.
16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16)
pages.
Regions can be individually protected or unprotected.
Additional protection of the Boot Loader pages.
Supports reads and writes of general-purpose NVM bits.
Supports reads and writes of additional NVM pages.
Supports device protection through a security bit.
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
Interface to Power Manager for power-down of flash-blocks in sleep mode.
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