AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 203

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.7.3.3
18.7.3.4
Figure 18-7. Programmable Delays
32059J–12/2010
Chip Select 1
Chip Select 2
Clock Generation
Transfer Delays
SPCK
The SPI Baud rate clock is generated by dividing the CLK_SPI by a value between 1 and 255.
This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud
rate of CLK_SPI divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead
to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first
transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the
SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud
rate for each interfaced peripheral without reprogramming.
Figure 18-7 on page 203
same chip select. Three delays can be programmed to modify the transfer waveforms:
• The delay between chip selects, programmable only once for all the chip selects by writing the
• The delay before SPCK, independently programmable for each chip select by writing the field
• The delay between consecutive transfers, independently programmable for each chip select by
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip
select and before assertion of a new one.
DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the
same chip select
DLYBCS
DLYBS
shows a chip select transfer change and consecutive transfers on the
DLYBCT
AT32UC3B
DLYBCT
203