AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 469

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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32059J–12/2010
NBUSYBK: Number of Busy Banks
DTSEQ: Data Toggle Sequence
SHORTPACKETI: Short Packet Interrupt
RXSTALLDI: Received STALLed Interrupt
CRCERRI: CRC Error Interrupt
OVERFI: Overflow Interrupt
NAKEDI: NAKed Interrupt
PERRI: Pipe Error Interrupt
TXSTPI: Transmitted SETUP Interrupt
This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit.
This field indicates the number of busy bank.
For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are
For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this
This field indicates the data PID of the current bank.
For OUT pipe, this field indicates the data toggle of the next packet that will be sent.
For IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
This bit is cleared when the SHORTPACKETIC bit is written to one.
This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe.
This bit is cleared when the RXSTALLDIC bit is written to one.
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if
This bit is cleared when the CRCERRIC bit is written to one.
This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is
This bit is cleared when the OVERFIC bit is written to one.
This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.
This bit is cleared when the NAKEDIC bit written to one.
This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to
This bit is cleared when the error source bit is cleared.
This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the
This bit is cleared when the TXSTPIC bit is written to one.
0
0
1
1
0
0
1
1
busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.
the TXSTPE bit is one.
triggered if the OVERFIE bit is one.
the UPERRn register to determine the source of the error.
TXSTPE bit is one.
NBUSYBK
DTSEQ
0
1
0
1
0
1
0
1
Number of busy bank
All banks are free.
1 busy bank
2 busy banks
reserved
Data toggle sequence
Data0
Data1
reserved
reserved
AT32UC3B
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