AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 574

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.5.2
26.5.3
26.6
26.6.1
26.6.2
32059J–12/2010
Functional Description
Clocks
Interrupts
How to Initialize the Module
Data Format
The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before
using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is
enabled in the Power Manager.
The ABDAC needs a separate clock for the D/A conversion operation. This clock,
GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre-
quency must be as follow:
where f
GCLK_ABDAC clock must have a frequency of 12.288MHz.
The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other.
The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC
interrupt requires the interrupt controller to be programmed first.
In order to use the Audio Bitstream DAC the product dependencies given in
page 573
and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.
The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream
DAC Control Register (CR.EN).
The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be
set whenever the ABDAC is ready to receive a new sample. A new sample value should be writ-
ten to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the
Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writ-
ing one to the corresponding bits in the Interrupt Clear Register (ICR).
The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can
be written to the least and most significant halfword of the Sample Data Register (SDR),
respectively.
An input value of 0x7FFF will result in an output voltage of approximately:
An Input value of 0x8000 will result in an output value of approximately:
s
is the samping rate of the data stream to convert. For f
must be resolved. Particular attention should be given to the configuration of clocks
V
V
OUT
OUT
(
(
0x7FFF
0x8000
)
)
f
GCLK
≈
≈
--------- - VDDIO
128
--------- - VDDIO
128
38
90
=
⋅
⋅
256
×
f
=
=
S
--------- - 3 3
128
--------- - 3 3
128
38
90
⋅
⋅
,
,
≈
≈
0
2
s
,
,
= 48 kHz this means that the
98V
32V
AT32UC3B
Section 26.5 on
574