ATTINY44A-SSN Atmel, ATTINY44A-SSN Datasheet - Page 93

• Manufacturer Part Number: ATTINY44A-SSN
• Description: IC MCU AVR 4KB FLASH 20MHZ 14SOI
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44A-SSN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.7.1
8183C–AVR–03/11
Compare Output Mode and Waveform Generation
Figure 12-5.
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x[1:0] bits are set. However, the OC1x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. See
and
The design of the Output Compare pin logic allows initialization of the OC1x state before the out-
put is enabled. Note that some COM1x[1:0] bit settings are reserved for certain modes of
operation. See
The COM1x[1:0] bits have no effect on the Input Capture unit.
The Waveform Generator uses the COM1x[1:0] bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM1x[1:0] = 0 tells the Waveform Generator that no action
on the OC1x Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 12-3 on page
Table 12-4 on page
A change of the COM1x[1:0] bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the 1x strobe bits.
COMnx1
COMnx0
FOCnx
clk
I/O
Table 12-4 on page 107
“Register Description” on page 106
Compare Match Output Unit, Schematic (non-PWM Mode)
Waveform
Generator
107.
107, and for phase correct and phase and frequency correct PWM refer to
for details.
Table 12-2 on page
D
D
D
PORT
DDR
OCnx
Table 12-2 on page
Q
Q
Q
ATtiny24A/44A/84A
107. For fast PWM mode refer to
1
0
107,
Table 12-3 on page 107
OCnx
Pin
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