PIC16F688-E/P Microchip Technology, PIC16F688-E/P Datasheet - Page 601

• Manufacturer Part Number: PIC16F688-E/P
• Description: IC MCU PIC FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTER
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 30-16: Example Master SSP I
Table 30-28:
Param.
Note 1: Maximum pin capacitance = 10 pF for all I
D102 ‡
1997 Microchip Technology Inc.
No.
100
101
102
103
106
107
109
110
90
91
92
§ This specification ensured by design. For the value required by the I
‡ These parameters are for design guidance only and are not tested, nor characterized.
2: A fast-mode I
“Appendix.”
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line. Parameter 102.+
SCL line is released.
Symbol Characteristic
T
T
T
T
T
T
T
SU
HD
HD
SU
SU
T
T
HIGH
LOW
T
Cb
T
BUF
SDA
Out
AA
SDA
In
:
SCL
:
:
:
:
R
F
DAT
STO
STA
STA
DAT
Example Master SSP I
Note: Refer to
Clock high time
Clock low time
SDA and SCL
rise time
SDA and SCL
fall time
START condition
setup time
START condition
hold time
Data input
hold time
Data input
setup time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
2
Section 30. Electrical Specifications
C-bus device can be used in a standard-mode I
90
103
Figure 30-1
91
109
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
2
2
C Bus Data Timing
C Bus Data Requirements
for load conditions.
parameter 107
100
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
2
C pins.
106
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
= 1000 + 250 = 1250 ns (for 100 kHz-mode) before the
20 + 0.1Cb
20 + 0.1Cb
101
109
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
)(BRG + 1) §
4.7 ‡
1.3 ‡
TBD
TBD
TBD
Min
250
100
—
—
—
—
—
—
—
—
0
0
107
2
C specification, please refer to
2
C-bus system, but
1000
3500
1000
Max
300
300
300
300
100
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
92
102
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first
clock pulse is generated
Note 2
Time the bus must be free
before a new transmis-
sion can start
parameter 107
110
Figure A-11
DS31030A-page 30-31
Conditions
of the
250 ns
30