PIC16F688-E/P Microchip Technology, PIC16F688-E/P Datasheet - Page 114

• Manufacturer Part Number: PIC16F688-E/P
• Description: IC MCU PIC FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTER
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
7.1
DS31007A-page 7-2
Introduction
The EEPROM data memory is readable and writable during normal operation (full V
This memory is not directly mapped in the register file space. Instead it is indirectly addressed
through the Special Function Registers. There are four SFRs used to read and write this memory.
These registers are:
• EECON1
• EECON2 (not a physically implemented register)
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM loca-
tion being accessed. The 8-bit EEADR register can access up to 256 locations of Data EEPROM.
The EEADR register can be thought of as the indirect addressing register of the Data EEPROM.
EECON1 contains the control bits, while EECON2 is the register used to initiate the read/write.
Some devices will implement less then the entire memory map. The address range always starts
at 0h, and goes throughout the memory available.
device memory sizes and the address range for those sizes.
Table 7-1:
The EEPROM data memory allows byte read and write. A byte write automatically erases the
location and writes the new data (erase before write). The EEPROM data memory is rated for
high erase/write cycles. The write time is controlled by an on-chip timer. The write-time will vary
with voltage and temperature as well as from chip to chip. Please refer to the AC specifications
for exact limits.
When the device is code protected, the CPU may continue to read and write the data EEPROM
memory. The device programmer can no longer access this memory.
Note 1: Presently, devices are only offered with 64
Data EEPROM
bytes of Data EEPROM.
Size
128
256
64
Possible Data EEPROM Memory Sizes
(1)
Address Range
0h - FFh
0h - 3Fh
0h - 7Fh
Table 7-1
shows some of the possible common
1997 Microchip Technology Inc.
DD
range).