EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 793

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

DS785UM1
28.1.1 Memory Map
28.1.2 Functional Description
The GPIO base address is 0x8084_0000. All registers are 8 bits wide and are aligned on
word boundaries. For all registers, the upper 24 bits are not modified when written and
always read zeros.
Each port has an 8-bit data register and an 8-bit direction register. The data direction register
controls whether each individual GPIO pin is an input or output. Writing to a data register only
affects the pins that are configured as outputs. Reading a data register returns the value on
the corresponding GPIO pins.
Ports A, B, and F also provide interrupt capability. The 16 interrupt sources from Ports A and
B are combined into a single signal GPIOINTR which is connected to the system interrupt
controller. All eight individual interrupt signals on Port F are available to the system interrupt
controller as GPIO0INTR through GPIO7INTR.
The interrupt properties of each of the GPIO pins on ports A, B, and F are individually
configurable. Each interrupt can be either high or low level sensitive or either positive or
negative edge triggered. It is also possible to enable debouncing on the Port A, B, and F
interrupts. Debouncing is implemented using a 2-bit shift register clocked by a 128 Hz clock.
There are seven additional registers for port A, B, and F:
• GPIO Interrupt Enable registers (GPIOAIntEn, GPIOBIntEn, GPIOFIntEn) control which
• GPIO Interrupt Type 1 registers (GPIOAIntType1, GPIOBIntType1, GPIOFIntType1)
• GPIO Interrupt Type 2 registers (GPIOAIntType2, GPIOBIntType2, GPIOFIntType2)
• GPIO End-Of-Interrupt registers (GPIOAEOI, GPIOBEOI, GPIOFEOI) are used to clear
• GPIO Debounce registers (GPIOADB, GPIOBDB, GPIOFDB) enable debouncing of
• Interrupt Status registers (IntStsA, IntStsB, IntStsF) provide the status of any pending
• Raw Interrupt Status registers (RawIntStsA, RawIntStsB, RawIntStsF) provide the status
bits are to be configured as interrupts. Setting a bit in this register configures the
corresponding pin as an interrupt input.
determines interrupt type. Setting a bit in this register configures the corresponding
interrupt as edge sensitive; clearing it makes it level sensitive.
determines interrupt polarity. Setting a bit in this register configures the corresponding
interrupt as rising edge or high level sensitive; clearing it configures the interrupt as
falling edge or low level sensitive.
specific bits in the interrupt Status Register. Writing a one to a bit will clear the
corresponding interrupt; writing a zero has no effect.
specific interrupts signals.
unmasked interrupt.
of any pending interrupt regardless of masking.
Copyright 2007 Cirrus Logic
EP93xx User’s Guide
GPIO Interface
28-3
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