EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 772

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

27
27-2
IDE Interface
EP93xx User’s Guide
27.2.1 Diagrams and State Machines
DMA
Controller
AHB Bus
HDMARDYn/
HSTROBE
DMACKn
IDE Pin
DMARQ
DIOWn/
DA[2:0]
DIORn/
DASPn
INTRQ
STOP
CS0n
CS1n
Processor
IDE Controller
Figure 27-1. IDE Interface Signal Connections
Type
GPIO
GPIO
INT
-
-
-
-
-
-
Table 27-1. IDE Host to IDE Interface Definition
Copyright 2007 Cirrus Logic
No. of
Pins
1
1
1
1
1
1
1
1
3
Chip select for device registers with base address 0x1F0
Chip select for device registers with base address 0x3F0
3-bit binary encoded address
Strobe signal to read device regs or data port/
Flow control signal for Ultra DMA data-in burst/
Flow control signal for Ultra DMA data-out burst
Strobe signal to write device regs or data port/
Terminates an Ultra DMA burst
DMA acknowledge to DMARQ to initiate DMA transfers
Signal to indicate that a device is active, or that Device 1 is
present
DMA request for DMA to and from the controller
Device interrupt
DIORn/HDMARDYn/HSTROBE
IORDY/DDMARDYn/DSTROBE
CS0n, CS1n
DIOWn/STOP
DMACKn
DA[2:0]
DD[15:0]
DMARQ
DASPn
INTRQ
Description
IDE Connector
DS785UM1