EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 124

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

4
4-6
Boot ROM
EP93xx User’s Guide
4.2.1 UART Boot
4.2.2 SPI Boot
4.2.3 FLASH Boot
Make sure that the boot configuration pins (see
internal boot mode. EEDAT and BOOT0 should be pulled high and BOOT1 should be pulled
low as shown in
No flow control. The code performs:
To boot from an SPI Serial Flash device, make sure that the boot configuration pins (see
Table 5-1 on page
and LBOOT1 and LBOOT0 should be pulled low as shown in
To boot from the SPI ROM, place the ASCII “CRUS” or “SURC” value in the HeaderID at the
first location in the ROM. The code will be copied from the SPI ROM to the Ethernet buffer at
address 0x8001_4000 with a length of 2048 bytes. Code execution will start at 0x8001_4000
(MAC base + 0x4000). The ARM Core will be in SVC mode. At this point the user can use the
code in the MAC buffer to load the rest of the image from the SPI ROM.
To enable FLASH boot, make sure that the boot configuration pins (see
2) are configured for normal boot mode, as shown in
FLASH word size is correct as shown in
To boot from FLASH, put the ASCII “CRUS” or “SURC” value in the HeaderID at one of the
following locations (this location will be referred to as FLASH base + 0x0):
0x1000_0000
0x2000_0000
0x3000_0000
0x6000_0000
0x7000_0000
Code execution will start at address FLASH base + 0x4. The ARM Core will be in SVC mode.
Alternatively, to boot from FLASH, put the ASCII “CRUS” or “SURC” value in the HeaderID at
one of the following locations (this location will be referred to as FLASH base +0x1000):
0x1000_1000
0x2000_1000
1. A single “<“ is output by UART 1
2. The ASCII “CRUS” or “SURC” value in the HeaderID is read
3. 2048 characters are received by UART 1 and copied to the Ethernet buffer at address
4. The ARM Core will jump to 0x8001_4000. The ARM Core will be in SVC mode when the
0x8001_4000
jump occurs.
Table 5-2 on page
5-2) are configured for internal boot mode. EEDAT should be pulled high
Copyright 2007 Cirrus Logic
5-3. UART 1 is configured at 9600 bps, 8-bits, No Parity,
Table
4-1.
Table 5-1 on page
Table
4-1. Also make sure that the
Table 5-2 on page
5-2) are configured for
Table 5-1 on page 5-
5-3.
DS785UM1